Vertical-transport transistors with self-aligned contacts

ABSTRACT

Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

BACKGROUND

The present invention relates to semiconductor device fabrication andintegrated circuits and, more specifically, to methods for forming avertical-transport field-effect transistor and structures for avertical-transport field-effect transistor.

Device structures for a field-effect transistor generally include a bodyregion, a source and a drain defined in the body region, and a gateelectrode configured to switch carrier flow in a channel formed in thebody region. When a control voltage exceeding a designated thresholdvoltage is applied to the gate electrode, carrier flow occurs in aninversion or depletion layer in the channel between the source and drainto produce a device output current. The body region and channel of aplanar field-effect transistor are located beneath the top surface of asubstrate on which the gate electrode is supported.

Planar field-effect transistors and fin-type field-effect transistorsconstitute a general category of transistor structures in which thedirection of gated current in the channel is in a horizontal directionparallel to the substrate surface. In a vertical-transport field-effecttransistor, the source and the drain are arranged at the top and bottomof a semiconductor fin or pillar. The direction of the gated currenttransport in the channel between the source and drain is generallyperpendicular (i.e., vertical) to the substrate surface and, therefore,parallel to the height of the semiconductor fin or pillar.

SUMMARY

In an embodiment, a method is provided for forming a vertical-transportfield-effect transistor. The method includes forming a semiconductor finthat projects from a first source/drain region, epitaxially growing asecond source/drain region that is spaced vertically along thesemiconductor fin from the first source/drain region, forming a gatestack arranged between the second source/drain region and the firstsource/drain region, and forming a spacer adjacent to a sidewall of thesecond source/drain region. The method further includes forming a firstcontact connected with a top surface of the second source/drain region,forming a second contact connected with a top surface of the firstsource/drain region, and forming a third contact connected with a topsurface of the gate stack. The spacer is arranged between the secondsource/drain region and the second contact or between the secondsource/drain region and the third contact.

In an embodiment, a structure is provided for a vertical-transportfield-effect transistor. The structure includes a first source/drainregion having a top surface, a semiconductor fin that projects from thetop surface of the first source/drain region, and a second source/drainregion that is spaced vertically along the semiconductor fin from thefirst source/drain region. The structure further includes a gate stackarranged between the second source/drain region and the firstsource/drain region, a spacer adjacent to a sidewall of the secondsource/drain region, a first contact connected with the top surface ofthe second source/drain region, a second contact connected with a topsurface of the first source/drain region, and a third contact connectedwith a top surface of the gate stack. The spacer is arranged between thesecond source/drain region and the second contact or between the secondsource/drain region and the third contact.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-7 are cross-sectional views showing a structure at successivefabrication stages of a processing method in accordance with embodimentsof the invention.

FIGS. 8-14 are cross-sectional views showing a structure at successivefabrication stages of a processing method in accordance with embodimentsof the invention.

DETAILED DESCRIPTION

With reference to FIG. 1 and in accordance with embodiments of theinvention, a fin 10 projects in a vertical direction from a bottomsource/drain region 12 and a fin 11 projects in a vertical directionfrom a bottom source/drain region 14. As used herein, the term“source/drain region” connotes a doped region of semiconductor materialthat can function as either a source or a drain of a vertical-transportfield-effect transistor. The fins 10, 11 and the bottom source/drainregions 12, 14 are used to form complementary vertical-transportfield-effect transistors as described hereinbelow. The fins 10, 11 maybe formed from an epitaxial layer of semiconductor material, such asundoped or intrinsic silicon, that is grown on the bottom source/drainregions 12, 14 and patterned using photolithography and etchingprocesses, such as a sidewall imaging transfer (SIT) process orself-aligned double patterning (SADP).

In connection with the formation of an n-type vertical-transport fieldeffect transistor 18, the bottom source/drain region 12 may be composedof silicon and include a concentration of an n-type dopant from Group Vof the Periodic Table (e.g., phosphorus (P) and/or arsenic (As)) thatimparts n-type electrical conductivity to the constituent semiconductormaterial. In connection with the formation of a p-typevertical-transport field effect transistor 20, the bottom source/drainregion 14 may be composed of a silicon-germanium (SiGe) alloy andinclude a concentration of p-type dopant from Group III of the PeriodicTable (e.g., boron (B), aluminum (Al), gallium (Ga), and/or indium (In))that imparts p-type electrical conductivity to the constituentsemiconductor material. A dielectric layer 16, which may be composed ofa dielectric material, such as an oxide of silicon (e.g., silicondioxide (SiO₂)), may electrically isolate the bottom source/drain region12 from the bottom source/drain region 14.

A bottom spacer layer 22 is arranged on the bottom source/drain regions12, 14. The bottom spacer layer 22 may be composed of a dielectricmaterial, such as silicon nitride (Si₃N₄), that is deposited by adirectional deposition technique, such as high-density plasma (HDP)deposition or gas cluster ion beam (GCIB) deposition. The fins 10, 11extend in the vertical direction through the thickness of the bottomspacer layer 22.

A gate dielectric layer 24 is arranged on the sidewalls of the fins 10,11. The gate dielectric layer 24 may be composed of a dielectricmaterial, such as a high-k dielectric having a dielectric constant(e.g., permittivity) higher than the dielectric constant of SiO₂.Candidate high-k dielectric materials for the gate dielectric layer 24include, but are not limited to, a hafnium-based dielectric materiallike hafnium oxide (HfO₂), a layered stack of a hafnium-based dielectricmaterial and another other dielectric material (e.g., aluminum oxide(Al₂O₃)), or combinations of these and other dielectric materials.

A gate stack 26 is arranged on the bottom spacer layer 22 and isseparated from the fins 10, 11 by the gate dielectric layer 24. The gatestack 26 may be composed of one or more conformal barrier metal layersand/or work function metal layers, such as titanium aluminum carbide(TiAlC), titanium nitride (TiN), cobalt (Co), tungsten (W), orcombinations of these and other metals. The layers of gate stack 26 maybe serially deposited by, for example, physical vapor deposition (PVD)or CVD, on the fins 10, 11 and etched back.

A top spacer layer 28 is arranged on the gate stack 26. The top spacerlayer 28 may be composed of a dielectric material, such as siliconnitride (Si₃N₄), that is deposited by a directional depositiontechnique, such as high-density plasma (HDP) deposition or gas clusterion beam (GCM) deposition. The fins 10, 11 extend in the verticaldirection through the thickness of the top spacer layer 28.

A top source/drain region 30 is arranged on the top surface of the fin10 that is exposed through the top spacer layer 28. A top source/drainregion 32 is arranged on the top surface of the fin 11 that is exposedthrough the top spacer layer 28. The top source/drain region 30 includessidewalls 27 that surround its circumference and the top source/drainregion 32 includes sidewalls 29 that surround its circumference. The topsource/drain regions 30, 32 may extend laterally to slightly overlie thegate stack 26 at their outer perimeters, and may be trimmed at theirsidewalls 27, 29 using a wet isotropic etching process to reduce theextent of these lateral extensions.

The top source/drain region 30 may be composed of semiconductor materialthat is doped to have the same conductivity type as the bottomsource/drain region 12. If the bottom source/drain region 12 is n-type,then the top source/drain region 30 may be a section of semiconductormaterial formed by an epitaxial growth process with in-situ doping, andmay include a concentration of an n-type dopant from Group V of thePeriodic Table (e.g., phosphorus (P) and/or arsenic (As)) that impartsn-type electrical conductivity to the constituent semiconductormaterial. The top source/drain region 32 may be composed ofsemiconductor material that is doped to have the same conductivity typeas the bottom source/drain region 14. If the bottom source/drain region14 is p-type, then the top source/drain region 32 may be a section ofsemiconductor material formed by an epitaxial growth process within-situ doping, and may include a concentration of a p-type dopant fromGroup III of the Periodic Table (e.g., boron (B), aluminum (Al), gallium(Ga), and/or indium (In)) that imparts p-type electrical conductivity tothe constituent semiconductor material. In an embodiment, the topsource/drain region 30 and the top source/drain region 32 may be formedby selective epitaxial growth (SEG) processes in which the constituentsemiconductor material nucleates for epitaxial growth on semiconductorsurfaces (e.g., fins 10, 11), but does not nucleate for epitaxial growthfrom insulator surfaces.

An interlayer dielectric layer 34 is applied that covers thefield-effect transistors. The interlayer dielectric layer 34 may becomposed of a dielectric material, such as an oxide of silicon (e.g.,silicon dioxide (SiO₂)) deposited by chemical vapor deposition (CVD).

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage, the interlayerdielectric layer 34 is recessed by an etch-back process with a timedetching process to reveal the sidewalls 27, 29 of the top source/drainregions 30, 32 and to reveal a section of the top spacer layer 28covering the gate stack 26. In an embodiment, the sidewalls 27, 29 ofthe top source/drain regions 30, 32 may be fully revealed.

Spacers 36 are arranged adjacent to the sidewalls 27 of the topsource/drain region 30, as well as adjacent to the sidewalls 29 of thetop source/drain region 32. The spacers 36 are formed after theinterlayer dielectric layer 34 is recessed. The spacers 36 may be formedby depositing a conformal layer comprised of a dielectric materialchosen to etch selective to the dielectric material constitutinginterlayer dielectric layer 34 and shaping the conformal layer with ananisotropic etching process, such as reactive ion etching (RIE). As usedherein, the term “selective” in reference to a material removal process(e.g., etching) connotes that the material removal rate (i.e., etchrate) for the targeted material is higher than the material removal rate(i.e., etch rate) for at least another material exposed to the materialremoval process. The spacers 36 may be composed of a nitride-basedmaterial, such as silicon nitride (Si₃N₄), silicon oxynitride (SiON),silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN), depositedby, for example, atomic layer deposition (ALD).

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage, a gap-filldielectric layer 38 is deposited and planarized to the top surfaces 31,33 of the top source/drain regions 30, 32 with, for example, chemicalmechanical processing (CMP) to fill the open spaces. The gap-filldielectric layer 38 may be composed of a dielectric material, such as anoxide of silicon (e.g., silicon dioxide (SiO₂)) deposited by chemicalvapor deposition (CVD). The top surfaces 31, 33 of the top source/drainregions 30, 32 are revealed by the planarization.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage, the topsurfaces 31, 33 of the top source/drain regions 30, 32 are recessedrelative to the spacers 36 and the top surface of the gap-filldielectric layer 38. The spacers 36 project above the recessed topsurfaces 31, 33. The etching process used to recess the top source/drainregions 30, 32 may remove the constituent semiconductor materialsselective to the materials constituting the spacers 36 and the gap-filldielectric layer 38. For example, the top source/drain regions 30, 32may be recessed relative to the top surface 37 of the gap-filldielectric layer 38 by one-third of their respective thicknesses. Spacesare formed above the top surface of the recessed top surfaces 31, 33 ofthe top source/drain regions 30, 32.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage, caps 40 areformed on the top surfaces 31, 33 (FIG. 4) of the top source/drainregions 30, 32 in the spaces opened when the top source/drain regions30, 32 are recessed. The caps 40 may be formed by depositing a gap-filllayer comprised of a dielectric material and planarizing the gap-filllayer to the top surface of the spacers 36 and the top surface 37 of thegap-fill dielectric layer 38 with, for example, CMP. The caps 40 may becomposed of a nitride-based material, such as silicon nitride (Si₃N₄),silicon oxynitride (SiON), silicon oxycarbide (SiOC), or siliconoxycarbonitride (SiOCN), deposited by ALD.

With reference to FIG. 6 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage, an interlayerdielectric layer 42 is formed that covers the field-effect transistors.The interlayer dielectric layer 42 may be composed of a dielectricmaterial, such as an oxide of silicon (e.g., silicon dioxide (SiO₂))deposited by chemical vapor deposition (CVD).

An opening 44 is formed in the dielectric layers 34, 38, 42 that extendsto the bottom source/drain region 12. The opening 44 may be formed byapplying an etch mask to the dielectric layer 42 and patterning thedielectric layers 34, 38, 42 with an etching process. The etch mask maybe stripped after the opening 44 is formed. The etching process may beone or more reactive ion etching (RIE) processes with etch chemistriesselected to etch the dielectric layers 34, 38, 42 and to punch throughthe dielectric material of the top spacer layer 28 covering the bottomsource/drain region 12. The opening 44 is self-aligned relative to thebottom source/drain region 12 by the spacers 36, which add extraprotection to the gate stack 26 and the top source/drain region 30during the etching process forming opening 44. The lithography processused to form the opening 44 has an enhanced tolerance to misalignmentand an improved overlay margin.

An opening 46 is formed in the dielectric layers 38, 42 that extends tothe gate stack 26. The opening 46 may be formed by applying an etch maskto the dielectric layer 42 and patterning the dielectric layers 38, 42with an etching process. The etch mask may include an organicplanarization layer (OPL) material applied by spin-coating that fillsthe opening 44, and that is stripped after the opening 46 is formed. Theetching process may be one or more reactive ion etching (RIE) processeswith etch chemistries selected to etch the dielectric layers 38, 42 andto punch through the dielectric material of the top spacer layer 28covering the gate stack 26. The opening 46 is self-aligned relative tothe gate stack 26 by the spacers 36, which add extra protection to thetop source/drain region 32 during the etching process forming opening46. The lithography process used to form the opening 46 has an enhancedtolerance to misalignment and an improved overlay margin.

Openings 48 are formed in the dielectric layer 42 that extend to the topsurface 31 of the top source/drain region 30 and to the top surface 33of the top source/drain region 32. The openings 48 may be formed byapplying an etch mask to the dielectric layer 42 and patterning thedielectric layer 42 and caps 40 with an etching process. The etch maskmay include an organic planarization layer (OPL) material applied byspin-coating that fills the openings 44, 46, and that is stripped afterthe openings 48 are formed. The etching process may be one or morereactive ion etching (RIE) processes with etch chemistries selected toetch the dielectric layer 42 and to punch through the dielectricmaterial of the caps 40 covering the top source/drain regions 30, 32.The remnants of the caps 40 define spacers located between the opening44 and the top source/drain regions 30, 32, as well as between theopening 46 and the top source/drain regions 30, 32. The spacers definedby the remnants of the caps 40 are also located between the opening 44and the opening 48, as well as between the opening 46 and the opening48.

With reference to FIG. 7 in which like reference numerals refer to likefeatures in FIG. 6 and at a subsequent fabrication stage, the openings44, 46, 48 (FIG. 6) in the dielectric layers 34, 38, and 42 are filledwith one or more conductors to respectively form contacts 54, 56, and58. The openings 44, 46, 48 may be lined with a barrier layer, followedby filling with, for example, a metal silicide and/or tungsten (W) toform the contacts 54, 56, 58. The contact 54 extends vertically to thebottom source/drain region 12. The contact 56 extends vertically to thegate stack 26. The contacts 58 extend vertically to the respective topsurfaces 31, 33 of the top source/drain regions 30, 32.

One of the spacers 36 and a spacer defined by a remnant of the cap 40 ontop source/drain region 30 are located between the contact 54 and thetop source/drain region 30. One of the spacers 36 and a spacer definedby a remnant of the cap 40 on top source/drain region 32 are locatedbetween the contact 56 and the top source/drain region 32. One of thespacers 36, a spacer defined by a remnant of the cap 40 on topsource/drain region 30, and a section of the dielectric layer 42 arelocated between the contact 54 and one of the contacts 58. One of thespacers 36, a spacer defined by a remnant of the cap 40 on topsource/drain region 30, and a section of the dielectric layer 42 arelocated between the contact 56 and the other of the contacts 58.

In an embodiment, all of the contacts 54, 56, 58 may be associated witha transistor formed using a single fin, e.g., fin 10 and having a singletop source/drain region, e.g., top source/drain region 30. Thearrangement of spacers, contacts, and the top source/drain region isunchanged in such an embodiment.

With reference to FIG. 8 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage in accordancewith alternative embodiments of the invention, the top surfaces 31, 33of the top source/drain regions 30, 32 are recessed relative to the topsurface of the gap-fill dielectric layer 38. The caps 40 are formed onthe top surfaces 31, 33 of the top source/drain regions 30, 32 in thespaces opened when the top source/drain regions 30, 32 are recessed.

With reference to FIG. 9 in which like reference numerals refer to likefeatures in FIG. 8 and at a subsequent fabrication stage, the interlayerdielectric layer 34 is recessed by an etch-back process with a timedetching process to reveal the sidewalls 27, 29 of the top source/drainregions 30, 32 and to reveal a section of the top spacer layer 28covering the gate stack 26. In an embodiment, the sidewalls 27, 29 ofthe top source/drain regions 30, 32 may be fully revealed. Afterrecessing the interlayer dielectric layer 34, the spacers 36 are formedadjacent to the sidewalls 27 of the top source/drain region 30, as wellas adjacent to the sidewalls 29 of the top source/drain region 32. Thespacers 36 may be formed by depositing a conformal layer comprised of adielectric material chosen to etch selective to the dielectric materialconstituting interlayer dielectric layer 34 and shaping the conformallayer with an anisotropic etching process, such as reactive ion etching(RIE). The spacers 36 may be composed of a nitride-based material, suchas silicon nitride (Si₃N₄), silicon oxynitride (SiON), siliconoxycarbide (SiOC), or silicon oxycarbonitride (SiOCN), deposited by, forexample, ALD. The gap-fill dielectric layer 38 is deposited andplanarized to the top surfaces 31, 33 of the top source/drain regions30, 32 with, for example, chemical mechanical processing (CMP) to fillthe open spaces.

With reference to FIG. 10 in which like reference numerals refer to likefeatures in FIG. 9 and at a subsequent fabrication stage, the interlayerdielectric layer 42 is formed that covers the field-effect transistors.The openings 48 are formed in the dielectric layer 42 that extend to thetop surface 31 of the top source/drain region 30 and to the top surface33 of the top source/drain region 32. The width of the openings 48 isincreased such that the caps 40 are removed in their entirety, which maybe accomplished with an etching process that removes the caps 40selective to the spacers 36. The openings 48 are formed before theopenings 44, 46 are formed.

With reference to FIG. 11 in which like reference numerals refer to likefeatures in FIG. 10 and at a subsequent fabrication stage, the contacts58 are formed in the openings 48 that extend vertically to therespective top surfaces 31, 33 of the top source/drain regions 30, 32.Following planarization, the dielectric layer 42 and contacts 48 arecoplanar at their top surfaces. The contacts 48 are fully strapped withthe top source/drain regions 30, 32 in that the complete removal of thecaps 40 permits the contacts 48 to touch or contact the entirety of therespective top surfaces of the top source/drain regions 30, 32.

With reference to FIG. 12 in which like reference numerals refer to likefeatures in FIG. 11 and at a subsequent fabrication stage, an etch mask60 is formed on the dielectric layer 42 and contacts 58. The etch mask60 may be composed of a layer of a light-sensitive material, such as anorganic photoresist, applied by a spin coating process, pre-baked,exposed to light projected through a photomask, baked after exposure,and developed with a chemical developer. Openings 62, 64 may be formedin the dielectric layer 42 and contacts 58 by an etching process, whichmay be a reactive ion etching (RIE) process or a wet chemical process,using a given etch chemistry.

The formation of the openings 62, 64 divides each of the contacts 58into a wide portion that is adjacent to the top source/drain regions 30,32 and a narrow portion that is separated from the top source/drainregions 30, 32 by the wide portion. The fully-strapped state of thecontacts with the top source/drain regions 30, 32 is maintained as thepenetration depth of the openings 62, 64 into the contacts 58 is limitedsuch that the openings 62, 64 do not penetrate through the full heightof the contacts 58. The openings 62, 64 also extend laterally in widthto overlap with the spacers 36.

With reference to FIG. 13 in which like reference numerals refer to likefeatures in FIG. 12 and at a subsequent fabrication stage, spacers 66,68 are formed in the openings 62, 64 in the dielectric layer 42. Thespacers 66, 68 may be composed of a nitride-based material, such assilicon nitride (Si₃N₄), silicon oxynitride (SiON), silicon oxycarbide(SiOC), or silicon oxycarbonitride (SiOCN), deposited by, for example,ALD and then planarized with CMP. The spacers 66 each overlap with oneof the spacers 36 to provide a solid dielectric barrier.

With reference to FIG. 14 in which like reference numerals refer to likefeatures in FIG. 13 and at a subsequent fabrication stage, the openings44 and 46 are formed in the dielectric layers 34, 38, and 42 and filledwith one or more conductors to respectively form the contacts 54 and 56.One of the spacers 36 and one of the spacers 66 are located between thecontact 54 and the top source/drain region 30. One of the spacers 36 andone of the spacers 66 are located between the contact 56 and the topsource/drain region 32. One of the spacers 36 and one of the spacers 66are located between the contact 54 and one of the contacts 58, and eachof the contacts 54, 58 may be in direct contact with the spacers 36, 66.One of the spacers 36 and one of the spacers 66 are located between thecontact 56 and the other of the contacts 58, and each of the contacts56, 58 may be in direct contact with the spacers 36, 66. Depending onthe alignment of the openings 44 and 46, the contacts 54 and 56 may belocated relative to the contacts 58 without an intervening section ofthe dielectric layer 42. In this instance, the spacers 66 directlycontact the contacts 54, 56, and 58.

In an embodiment, all of the contacts 54, 56, 58 may be associated witha transistor formed using a single fin, e.g., fin 10 and having a singletop source/drain region, e.g., top source/drain region 30. Thearrangement of spacers, contacts, and the top source/drain region isunchanged in such an embodiment.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (e.g., as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (e.g., aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (e.g., a ceramic carrierthat has either or both surface interconnections or buriedinterconnections). In any case, the chip may be integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either an intermediate product or an end product.

References herein to terms such as “vertical”, “horizontal”, “lateral”,etc. are made by way of example, and not by way of limitation, toestablish a frame of reference. Terms such as “horizontal” and “lateral”refer to a direction in a plane parallel to a top surface of asemiconductor substrate, regardless of its actual three-dimensionalspatial orientation. Terms such as “vertical” and “normal” refer to adirection perpendicular to the “horizontal” and “lateral” direction.Terms such as “above” and “below” indicate positioning of elements orstructures relative to each other and/or to the top surface of thesemiconductor substrate as opposed to relative elevation.

A feature “connected” or “coupled” to or with another element may bedirectly connected or coupled to the other element or, instead, one ormore intervening elements may be present. A feature may be “directlyconnected” or “directly coupled” to another element if interveningelements are absent. A feature may be “indirectly connected” or“indirectly coupled” to another element if at least one interveningelement is present.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method of forming a vertical-transportfield-effect transistor, the method comprising: forming a semiconductorfin that projects from a first source/drain region; epitaxially growinga second source/drain region that is spaced vertically along thesemiconductor fin from the first source/drain region; forming a gatestack arranged between the second source/drain region and the firstsource/drain region; forming a first spacer adjacent to a first sidewallof the second source/drain region; forming a second spacer adjacent to asecond sidewall of the second source/drain region; after forming thefirst spacer and the second spacer, recessing a top surface of thesecond source/drain region; forming a dielectric cap on the top surfaceof the second source/drain region; forming a first contact extendingthrough the dielectric cap and connected with a top surface of thesecond source/drain region; forming a second contact connected with atop surface of the first source/drain region; and forming a thirdcontact connected with a top surface of the gate stack, wherein thefirst spacer is arranged between the second source/drain region and thesecond contact or between the second source/drain region and the thirdcontact.
 2. The method of claim 1 wherein the first spacer and thesecond spacer are concurrently formed.
 3. The method of claim 1 whereinforming the dielectric cap comprises: depositing a dielectric materialin a space above the top surface of the second source/drain region thatis interior of the first spacer and the second spacer to form thedielectric cap.
 4. The method of claim 1 wherein the first spacer isarranged between the second source/drain region and the second contact,and the second contact is in direct contact with the first spacer. 5.The method of claim 1 wherein the first spacer is arranged between thesecond source/drain region and the third contact, and the third contactis in direct contact with the first spacer.
 6. A method of forming avertical-transport field-effect transistor, the method comprising:forming a semiconductor fin that projects from a first source/drainregion; epitaxially growing a second source/drain region that is spacedvertically along the semiconductor fin from the first source/drainregion; forming a gate stack arranged between the second source/drainregion and the first source/drain region; recessing a top surface of thesecond source/drain region; forming a dielectric cap on the top surfaceof the second source/drain region; after the dielectric cap is formed,forming a first spacer adjacent to a first sidewall of the secondsource/drain region; forming a first contact connected with a topsurface of the second source/drain region; forming a second contactconnected with a top surface of the first source/drain region; andforming a third contact connected with a top surface of the gate stack,wherein the first spacer is arranged between the second source/drainregion and the second contact or between the second source/drain regionand the third contact.
 7. The method of claim 1 wherein the secondsource/drain region is formed in a dielectric layer, and forming thefirst spacer adjacent to the first sidewall of the second source/drainregion comprises: recessing the dielectric layer to reveal the firstsidewall of the second source/drain region.
 8. The method of claim 6wherein the first spacer is arranged between the second source/drainregion and the second contact, and further comprising: forming a secondspacer adjacent to a second sidewall of the second source/drain region,wherein the second spacer is arranged between the second source/drainregion and the third contact.
 9. The method of claim 6 wherein the firstspacer is arranged between the second source/drain region and the thirdcontact, and further comprising: forming a second spacer adjacent to asecond sidewall of the second source/drain region, wherein the secondspacer is arranged between the second source/drain region and the secondcontact.
 10. The method of claim 6 wherein the first spacer is arrangedbetween the second source/drain region and the second contact, and thesecond contact is in direct contact with the first spacer.
 11. Themethod of claim 6 wherein the first spacer is arranged between thesecond source/drain region and the third contact, and the third contactis in direct contact with the first spacer.
 12. The method of claim 6wherein the second source/drain region is formed in a dielectric layer,and forming the first spacer adjacent to the first sidewall of thesecond source/drain region comprises: recessing the dielectric layer toreveal the first sidewall of the second source/drain region.
 13. Themethod of claim 6 wherein forming the first contact connected with thetop surface of the second source/drain region further comprises: beforeforming the first contact, completely removing the dielectric cap fromthe top surface of the second source/drain region, wherein the firstcontact includes a first portion that directly contacts an entirety ofthe top surface of the second source/drain region.
 14. The method ofclaim 8 wherein the first spacer and the second spacer are concurrentlyformed.
 15. The method of claim 8 wherein forming the dielectric capcomprises: depositing a dielectric material in a space above the topsurface of the second source/drain region that is interior of the firstspacer and the second spacer to form the dielectric cap.
 16. The methodof claim 9 wherein the first spacer and the second spacer areconcurrently formed.
 17. The method of claim 13 further comprising:narrowing a second portion of the first contact that is arranged overthe first portion of the first contact; and forming a second spacerarranged adjacent to the second portion of the first contact and overthe first portion of the first contact.
 18. The method of claim 17wherein the second spacer is arranged between the first contact and thesecond contact after the second contact is formed, and the first contactand the second contact are in direct contact with the second spacer. 19.The method of claim 17 wherein the second spacer is arranged between thefirst contact and the third contact after the third contact is formed,and the first contact and the third contact are in direct contact withthe second spacer.